In modern computer systems, demand for memory capacity and bandwidth keeps growing. Recent performance scaling of microprocessors relies on increasing the number of cores per chip, and multi-core and many core chip multi-processors (“CMP”) demand even higher memory bandwidth and capacity through multiple memory controllers per processor. So the power budget of main memory modules becomes similar to or even higher than that of processors in current computer systems.
However, typical memory modules are energy inefficient. For example, the standby energy of memory modules is a significant portion of total main memory energy usage when multiple memory modules are connected to a memory controller of a processor. When the memory modules are not actively responding to a memory request, most of the memory modules are idle using standby energy while they wait for the next memory request, which is an inefficient use of energy. Multiple power-down modes are provided in many current memory chips to save standby energy, and both system-software and hardware use these power-down modes to save standby energy. However, the amount of power saving is limited since the same power-down mode must be applied to all memory chips within the module.
Memory systems and methods enabling access to information stored in the memory system that saves energy without significantly sacrificing system performance are desired.